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document # sram124 rev a revised october 2005 p4c1024 high speed 128k x 8 dual chip enable cmos static ram the p4c1024 device provides asynchronous opera- tions with matching access and cycle times. memory locations are specified on address pins a 0 to a 16 . reading is accomplished by device selection ( ce 1 low and ce 2 high) and output enabling ( oe ) while write enable ( we ) remains high. by presenting the ad- dress under these conditions, the data in the ad- dressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce 1 or oe is high or we or ce 2 is low. the p4c1024 is a 1,048,576-bit high-speed cmos static ram organized as 128kx8. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. access times of 15 nanoseconds permit greatly en- hanced system operating speeds. cmos is utilized to reduce power consumption to a low level. the p4c1024 is a member of a family of pace ram? products offer- ing fast access times. advanced cmos technology fast t oe automatic power down packages ?32-pin 300 mil dip and soj ?32-pin 400 mil soj ?32-pin 600 mil ceramic dip ?32-pin 400 mil ceramic dip ?32-pin solder seal flatpack ?32-pin lcc (450 x 550 mil) ?32-pin ceramic soj high speed (equal access and cycle times) ? 15/20/25/35 ns (commercial) ? 20/25/35/45 ns (industrial) ? 20/25/35/45/55/70/85/100/120 ns (military) single 5 volts 10% power supply easy memory expansion using ce ce ce ce ce 1, ce 2 and oe oe oe oe oe inputs common data i/o three-state outputs fully ttl compatible inputs and outputs functional block diagram pin configuration description features dip (p300, c10, c11), soj (j300, j400, cj1), solder seal flatpack (fs-3) similar lcc (l6)
p4c1024 page 2 of 14 document # sram124 rev a maximum ratings (1) symbol parameter value unit v cc power supply pin with ?0.5 to +7 v respect to gnd terminal voltage with ?0.5 to v term respect to gnd v cc +0.5 v (up to 7.0v) t a operating temperature ?55 to +125 c symbol parameter value unit t bias temperature under ?55 to +125 c bias t stg storage temperature ?65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma recommended operating temperature and supply voltage i sb standby power supply current (ttl input levels) ce 1 v ih or mil. ce 2 v il , ind./com?l. v cc = max, f = max., outputs open ___ ___ 35 30 ___ ___ ___ ___ 25 20 25 n/a 2 n/a ma ma ___ ___ ce 1 v hc or mil. ce 2 v lc , ind./com?l. v cc = max, f = 0, outputs open v in v lc or v in v hc standby power supply current (cmos input levels) i sb1 grade (2) ambient temperature gnd v cc 0v 0v 5.0v 10% 5.0v 10% 0v 5.0v 10% ?55c to +125c military symbol c in c out parameter input capacitance output capacitance conditions v in = 0v v out = 0v 8 10 unit pf pf capacitances (4) v cc = 5.0v, t a = 25c, f = 1.0mhz symbol dc electrical characteristics over recommended operating temperature and supply voltage (2) v ih v il v hc v lc v cd v ol v oh i li i lo parameter input high voltage input low voltage cmos input high voltage cmos input low voltage input clamp diode voltage output low voltage (ttl load) output high voltage (ttl load) input leakage current output leakage current test conditions v cc = min., i in = ?18 ma i ol = +8 ma, v cc = min. i oh = ?4 ma, v cc = min. v cc = max. mil. v in = gnd to v cc ind./com?l. v cc = max., ce = v ih , mil. v out = gnd to v cc ind./com?l. p4c1024 min 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?10 ?5 ?10 ?5 max v cc +0.5 0.8 v cc +0.5 0.2 ?1.2 0.4 +10 +5 +10 +5 p4c1024l min max 2.2 ?0.5 (3) v cc ?0.2 ?0.5 (3) 2.4 ?5 n/a ?5 n/a v cc +0.5 0.8 v cc +0.5 0.2 0.4 ?1.2 +5 n/a +5 n/a unit v v v v v v v a a notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. transient inputs with v il and i il not more negative than ?3.0v and ?100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. typ. industrial commercial ?40c to +85c 0c to +70c
p4c1024 page 3 of 14 document # sram124 rev a data retention characteristics (p4c1024l, military temperature only) typ.* max symbol parameter test condition min v cc =v cc =unit 2.0v 3.0v 2.0v 3.0v v dr v cc for data retention 2.0 v i ccdr data retention current 50 200 400 600 a t cdr chip deselect to ns data retention time t r ? operation recovery time t rc ns * t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested. *v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce 1 = v il , ce 2 = v ih , oe = v ih power dissipation characteristics vs. speed data retention waveform ce 1 v cc ? 0.2v or ce 2 0.2v, v in v cc ? 0.2v or v in 0.2v symbol parameter temperature range -15 -20 -25 -35 -45 -55 -70 -85 -100 -120 unit commercial 190 160 150 145 n/a n/a n/a n/a n/a n/a ma industrial n/a 175 165 160 155 n/a n/a n/a n/a n/a ma military n/a 150 140 135 130 125 115 110 105 100 ma dynamic operating current* i cc
p4c1024 page 4 of 14 document # sram124 rev a ac electrical characteristics?read cycle (v cc = 5v 10%, all temperature ranges) (2) min max min max min max min max min max min max min max min max min max min max t rc read cycle time 15 20 25 35 45 55 70 85 100 120 ns t aa address access time 15 20 25 35 45 55 70 85 100 120 ns t ac chip enable access time 15 20 25 35 45 55 70 85 100 120 ns t oh output hold from address change 3333333333ns t lz chip enable to output in low z 3333333333ns t hz chip disable to output in high z 8 9 11 15 20 25 30 35 40 50 ns t oe output enable low to data valid 7 9 11 15 20 25 30 35 40 50 ns t olz output enable low to low z 0000000000ns t ohz output enable high to high z 7 9 11 15 20 25 30 35 40 50 ns t pu chip enable to power up time 0000000000ns t pd chip disable to power down time 12 20 20 20 25 30 35 40 45 50 ns symbol parameter -15 -20 -25 -35 -45 unit -55 -70 -85 -100 -120 notes: 5. we is high for read cycle. 6. ce 1 is low, ce 2 is high and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce 1 transition low and ce 2 transition high. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specified in figure 1. this parameter is sampled and not 100% tested. timing waveform of read cycle no. 1 ( oe oe oe oe oe controlled) (5)
p4c1024 page 5 of 14 document # sram124 rev a timinig waverform of read cycle no. 2 (address controlled) (5,6) timing waveform of read cycle no. 3 ( ce ce ce ce ce 1 , ce 2 controlled) (5,7,10) notes: 9. read cycle time is measured from the last valid address to the first transitioning address. 10. transitions caused by a chip enable control have similar delays irrespective of whether ce 1 or ce 2 causes them.
p4c1024 page 6 of 14 document # sram124 rev a ac characteristics?write cycle (v cc = 5v 10%, all temperature ranges) (2) min max min max min max min max min max min max min max min max min max min max t wc write cycle time 15 20 25 35 45 55 70 85 100 120 ns t cw chip enable time to end of write 12 15 18 22 30 35 45 50 60 75 ns t aw address valid to end of write 12 15 20 25 35 45 60 70 85 100 ns t as address set-up time 0000000000ns t wp write pulse width 12 15 18 22 25 30 40 45 55 70 ns t ah address hold time 0000000000ns t dw data valid to end of write 7 8 10 15 20 25 30 35 45 60 ns t dh date hold time0000000000ns t wz write enable to output in high z 8 101115182025304050ns t ow output active from end of write 3333333333ns symbol parameter -15 -20 -25 -35 -45 unit -55 -70 -85 -100 -120 notes: 11. ce 1 and we must be low, and ce 2 high for write cycle. 12. oe is low for this write cycle to show t wz and t ow . 13. if ce 1 goes high, or ce 2 goes low, simultaneously with we high, the output remains in a high impedance state. 14. write cycle time is measured from the last valid address to the first transitioning address. timing waveform of write cycle no. 1 ( we we we we we controlled) (11)
p4c1024 page 7 of 14 document # sram124 rev a timing waveform of write cycle no. 2 ( ce ce ce ce ce controlled) (11) 1.5v write active read * including scope and test fixture. note: because of the ultra-high speed of the p4c1024, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. long high- inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fingers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal reflections, proper termination must be used; for example, a 50 ? test environment should be terminated into a 50 ? load with 1.73v (thevenin voltage) at the comparator input, and a 116 ? resistor must be used in series with d out to match 166 ? (thevenin resistance). ac test conditions truth table input pulse levels input rise and fall times input timing reference level output timing reference level output load gnd to 3.0v 3ns 1.5v see fig. 1 and 2 mode standby standby d out disabled standby power i/o we we we we we oe oe oe oe oe ce 2 ce ce ce ce ce 1 high z high z d out high z x x h h l x x h l x x l h h h h x l l l standby active active high z figure 1. output load figure 2. thevenin equivalent
p4c1024 page 8 of 14 document # sram124 rev a ordering information selection guide the p4c1024 is available in the following temperature, speed and package options. 15 20 25 35 45 plastic dip (300 mil) -15p3c -20p3c -25p3c -35p3c n/a plastic soj (300 mil) -15j3c -20j3c -25j3c -35j3c n/a plastic soj (400 mil) -15j4c -20j4c -25j4c -35j4c n/a plastic dip (300 mil) n/a -20p3i -25p3i -35p3i -45p3i plastic soj (300 mil) n/a -20j3i -25j3i -35j3i -45j3i plastic soj (400 mil) n/a -20j4i -25j4i -35j4i -45j4i ceramic dip (600 mil) n/a -20c6m -25c6m -35c6m -45c6m ceramic dip (400 mil) n/a -20c4m -25c4m -35c4m -45c4m solder seal flatpack n/a -20fsm -25fsm -35fsm -45fsm lcc (450 x 550 mil) n/a -20lm -25lm -35lm -45lm ceramic soj n/a -20cjm -25cjm -35cjm -45cjm ceramic dip (600 mil) n/a -20c6mb -25c6mb -35c6mb -45c6mb ceramic dip (400 mil) n/a -20c4mb -25c4mb -35c4mb -45c4mb solder seal flatpack n/a -20fsmb -25fsmb -35fsmb -45fsmb lcc (450 x 550 mil) n/a -20lmb -25lmb -35lmb -45lmb ceramic soj n/a -20cjmb -25cjmb -35cjmb -45cjmb military processed* commercial speed military temperature temperature range package industrial * military temperature range with mil-std-883, class b compliance. n/a = not available
p4c1024 page 9 of 14 document # sram124 rev a * military temperature range with mil-std-883, class b compliance. n/a = not available 55 70 85 100 120 plastic dip (300 mil) n/a n/a n/a n/a n/a plastic soj (300 mil) n/a n/a n/a n/a n/a plastic soj (400 mil) n/a n/a n/a n/a n/a plastic dip (300 mil) n/a n/a n/a n/a n/a plastic soj (300 mil) n/a n/a n/a n/a n/a plastic soj (400 mil) n/a n/a n/a n/a n/a ceramic dip (600 mil) -55c6m -70c6m -85c6m -100c6m -120c6m ceramic dip (400 mil) -55c4m -70c4m -85c4m -100c4m -120c4m solder seal flatpack -55fsm -70fsm -85fsm -100fsm -120fsm lcc (450 x 550 mil) -55lm -70lm -85lm -100lm -120lm ceramic soj -55cjm -70cjm -85cjm -100cjm -120cjm ceramic dip (600 mil) -55c6mb -70c6mb -85c6mb -100c6mb -120c6mb ceramic dip (400 mil) -55c4mb -70c4mb -85c4mb -100c4mb -120c4mb solder seal flatpack -55fsmb -70fsmb -85fsmb -100fsmb -120fsmb lcc (450 x 550 mil) -55lmb -70lmb -85lmb -100lmb -120lmb ceramic soj -55cjmb -70cjmb -85cjmb -100cjmb -120cjmb commercial speed military processed* military temperature temperature range package industrial
p4c1024 page 10 of 14 document # sram124 rev a pkg # # pins symbol min max a 0.128 0.148 a1 0.082 - b 0.016 0.020 c 0.007 0.010 d 0.820 0.830 e e e1 0.295 0.305 e2 q0.025- j300 32 (300 mil) 0.050 bsc 0.267 bsc 0.335 bsc pkg # # pins symbol min max a 0.128 0.148 a1 0.082 - b 0.015 0.020 c 0.007 0.013 d 0.820 0.830 e e 0.435 0.445 e1 0.395 0.405 e2 q0.025- j400 32 (400 mil) 0.050 bsc 0.370 bsc soj small outline ic package (300 mil) soj small outline ic package (400 mil)
p4c1024 page 11 of 14 document # sram124 rev a pkg # # pins symbol min max a - 0.200 a1 0.015 - b 0.014 0.022 b2 0.048 0.054 c 0.008 0.014 d 1.580 1.620 e1 0.270 0.300 e 0.300 0.310 e eb 0.320 0.390 l 0.120 0.140 0 15 p300 32 (300 mil) 0.100 bsc plastic dual in-line package solder seal flat package pkg # # pins symbol min max a 0.097 0.125 b 0.015 0.019 c 0.003 0.009 d - 0.830 e 0.400 0.420 e1 - 0.450 e2 0.180 - e3 0.030 - e l 0.250 0.370 q 0.020 0.045 s - 0.045 s1 0.000 - m - 0.0015 n fs-3 32 0.050 bsc 32
p4c1024 page 12 of 14 document # sram124 rev a sidebrazed dual in-line package (600 mil) sidebrazed dual in-line package (400 mil) pkg # # pins symbol min max a-0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d-1.680 e 0.510 0.620 ea e l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - 0.600 bsc 0.100 bsc c10 32 (600 mil) pkg # # pins symbol min max a-0.232 b 0.014 0.023 b2 0.038 0.065 c 0.008 0.018 d-1.700 e 0.350 0.410 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - c11 32 (400 mil) 0.400 bsc 0.100 bsc
p4c1024 page 13 of 14 document # sram124 rev a pkg # # pins symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.442 0.458 d1 d2 d3 - 0.458 e 0.540 0.560 e1 e2 e3 - 0.558 e h j l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd ne l6 32 0.300 bsc 0.150 bsc 0.020 ref 7 9 0.400 bsc 0.200 bsc 0.050 bsc 0.040 ref rectangular leadless chip carrier ceramic soj small outline ic package pkg # # pins symbol min max a 0.120 0.165 a1 0.088 0.120 a2 0.070 ref b0.010ref b1 0.030r typ b2 0.020 ref b3 0.025 0.045 d 0.816 0.838 d1 0.750 ref e 0.419 0.431 e1 0.430 0.445 e2 0.360 0.380 e e1 0.038 typ e2 0.005 j0.005typ s 0.030 0.040 s1 0.020 typ cj1 32 0.050 bsc
p4c1024 page 14 of 14 document # sram124 rev a revisions document number : sram124 document title : p4c1024 high speed 128k x 8 dual chip enable cmos static ram rev. issue date orig. of change description of change or 1997 dab new data sheet a oct-05 jdb change logo to pyramid

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